| /u-boot/arch/arm/mach-tegra/tegra114/ |
| A D | clock.c | 667 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
668 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
677 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
682 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
701 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
704 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
705 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
745 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
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| /u-boot/arch/arm/mach-tegra/ |
| A D | clock.c | 693 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); in clock_init()
705 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); in clock_init()
770 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8); in tegra30_set_up_pllp()
775 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in tegra30_set_up_pllp()
780 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in tegra30_set_up_pllp()
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| /u-boot/arch/arm/mach-tegra/tegra124/ |
| A D | clock.c | 847 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
848 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
857 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
862 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
867 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
881 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
884 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()
885 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
1171 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
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| /u-boot/arch/arm/include/asm/arch-tegra20/ |
| A D | clock-tables.h | 15 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, enumerator
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| /u-boot/arch/arm/mach-tegra/tegra20/ |
| A D | clock.c | 592 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
597 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
602 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
762 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
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| /u-boot/arch/arm/mach-tegra/tegra210/ |
| A D | clock.c | 989 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
994 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
999 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
1003 clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0); in clock_early_init()
1007 clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0); in clock_early_init()
1020 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, in clock_early_init()
1028 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1], in clock_early_init()
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| /u-boot/arch/arm/include/asm/arch-tegra114/ |
| A D | clock-tables.h | 14 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, enumerator
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| /u-boot/arch/arm/include/asm/arch-tegra30/ |
| A D | clock-tables.h | 14 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, enumerator
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| /u-boot/drivers/video/ |
| A D | tegra.c | 137 rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL); in update_display_mode()
284 clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL, in tegra_display_probe()
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| /u-boot/arch/arm/include/asm/arch-tegra124/ |
| A D | clock-tables.h | 15 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, enumerator
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| /u-boot/arch/arm/include/asm/arch-tegra210/ |
| A D | clock-tables.h | 15 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, enumerator
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| /u-boot/arch/arm/mach-tegra/tegra30/ |
| A D | clock.c | 809 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
|