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Searched refs:CM_REG_READL (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/clk/altera/
A Dclk-agilex.c119 req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM); in membus_wait_for_req()
121 req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM); in membus_wait_for_req()
127 req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM); in membus_wait_for_req()
179 *rdata = CM_REG_READL(plat, CLKMGR_MAINPLL_MEMSTAT); in membus_read_pll()
181 *rdata = CM_REG_READL(plat, CLKMGR_PERPLL_MEMSTAT); in membus_read_pll()
351 reg = CM_REG_READL(plat, pllglob_reg); in clk_get_vco_clk_hz()
393 u32 clksrc = CM_REG_READL(plat, reg); in clk_get_5_1_clk_src()
407 clock /= (CM_REG_READL(plat, main_reg) & in clk_get_clksrc_hz()
413 clock /= (CM_REG_READL(plat, per_reg) & in clk_get_clksrc_hz()
517 ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL); in clk_get_emac_clk_hz()
[all …]
A Dclk-agilex.h13 #define CM_REG_READL(plat, reg) \ macro

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