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Searched refs:CONFIG_NR_DRAM_BANKS (Results 1 – 25 of 842) sorted by relevance

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/u-boot/arch/arm/lib/
A Dbootm-fdt.c41 u64 start[CONFIG_NR_DRAM_BANKS]; in arch_fixup_fdt()
42 u64 size[CONFIG_NR_DRAM_BANKS]; in arch_fixup_fdt()
44 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { in arch_fixup_fdt()
55 ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); in arch_fixup_fdt()
/u-boot/board/cirrus/edb93xx/
A Dedb93xx.c131 unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS]) in dram_fill_bank_addr() argument
156 (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) { in dram_fill_bank_addr()
179 unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS]; in dram_init_banksize_int()
195 for (; i < CONFIG_NR_DRAM_BANKS; i++) { in dram_init_banksize_int()
205 if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) { in dram_init_banksize_int()
209 CONFIG_NR_DRAM_BANKS, dram_bank_cnt); in dram_init_banksize_int()
210 dram_bank_cnt = CONFIG_NR_DRAM_BANKS; in dram_init_banksize_int()
/u-boot/board/kontron/sl28/
A Dsl28.c57 u64 base[CONFIG_NR_DRAM_BANKS]; in ft_board_setup()
58 u64 size[CONFIG_NR_DRAM_BANKS]; in ft_board_setup()
59 int nbanks = CONFIG_NR_DRAM_BANKS; in ft_board_setup()
A Dspl_atf.c24 struct region_info region[CONFIG_NR_DRAM_BANKS];
37 dram_regions_info.num_dram_regions = CONFIG_NR_DRAM_BANKS; in bl2_plat_get_bl31_params_v2()
38 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { in bl2_plat_get_bl31_params_v2()
/u-boot/include/configs/
A Dxenguest_arm64.h14 #undef CONFIG_NR_DRAM_BANKS
17 #define CONFIG_NR_DRAM_BANKS 1 macro
A Drk3036_common.h28 #define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE)
/u-boot/arch/x86/lib/
A Dbootm.c59 u64 start[CONFIG_NR_DRAM_BANKS]; in arch_fixup_memory_node()
60 u64 size[CONFIG_NR_DRAM_BANKS]; in arch_fixup_memory_node()
62 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { in arch_fixup_memory_node()
67 return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); in arch_fixup_memory_node()
/u-boot/common/init/
A Dhandoff.c21 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { in handoff_save_dram()
37 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { in handoff_load_dram_banks()
/u-boot/arch/arm/mach-octeontx2/
A Dcpu.c19 #define OTX2_MEM_MAP_MAX (OTX2_MEM_MAP_USED + CONFIG_NR_DRAM_BANKS + 1)
56 for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { in mem_map_fill()
/u-boot/arch/arm/mach-k3/
A Darm64-mmu.c18 #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
73 #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
131 #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
/u-boot/arch/arm/mach-octeontx/
A Dcpu.c19 #define OTX_MEM_MAP_MAX (OTX_MEM_MAP_USED + 1 + CONFIG_NR_DRAM_BANKS + 1)
60 for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { in mem_map_fill()
/u-boot/drivers/bootcount/
A Dbootcount_ram.c30 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) in bootcount_store()
53 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) in bootcount_load()
/u-boot/board/samsung/arndale/
A Darndale.c48 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { in dram_init()
66 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { in dram_init_banksize()
/u-boot/arch/arm/cpu/arm926ejs/armada100/
A Ddram.c81 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { in dram_init()
97 for (; i < CONFIG_NR_DRAM_BANKS; i++) { in dram_init()
/u-boot/api/
A Dapi_platform-arm.c31 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) in platform_sys_info()
/u-boot/arch/arm/mach-tegra/
A Darm64-mmu.c15 struct mm_region tegra_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
/u-boot/arch/arm/mach-versal/
A Dcpu.c21 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
83 for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { in mem_map_fill()
/u-boot/arch/x86/cpu/coreboot/
A Dsdram.c113 if (CONFIG_NR_DRAM_BANKS) { in dram_init_banksize()
121 if (j >= CONFIG_NR_DRAM_BANKS) in dram_init_banksize()
/u-boot/include/
A Dhandoff.h26 } ram_bank[CONFIG_NR_DRAM_BANKS];
/u-boot/configs/
A Dbcm958712k_defconfig4 CONFIG_NR_DRAM_BANKS=2
A Dqemu-riscv32_defconfig2 CONFIG_NR_DRAM_BANKS=1
A Dqemu-riscv32_smode_defconfig2 CONFIG_NR_DRAM_BANKS=1
A Dqemu-riscv32_spl_defconfig2 CONFIG_NR_DRAM_BANKS=1
A Dqemu-riscv64_defconfig2 CONFIG_NR_DRAM_BANKS=1
A Dqemu-riscv64_smode_defconfig2 CONFIG_NR_DRAM_BANKS=1

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