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Searched refs:CONFIG_ROCKCHIP_STIMER_BASE (Results 1 – 15 of 15) sorted by relevance

/u-boot/arch/arm/mach-rockchip/
A Dtpl.c29 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in rockchip_stimer_init()
39 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in rockchip_stimer_init()
40 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); in rockchip_stimer_init()
41 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); in rockchip_stimer_init()
42 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + in rockchip_stimer_init()
A Drk3036-board-spl.c25 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in rockchip_stimer_init()
26 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); in rockchip_stimer_init()
27 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); in rockchip_stimer_init()
28 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + in rockchip_stimer_init()
A Dpx30-board-tpl.c29 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in secure_timer_init()
30 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT0); in secure_timer_init()
31 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT1); in secure_timer_init()
33 CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in secure_timer_init()
A Dspl.c84 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in rockchip_stimer_init()
92 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in rockchip_stimer_init()
93 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); in rockchip_stimer_init()
94 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); in rockchip_stimer_init()
95 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + in rockchip_stimer_init()
/u-boot/arch/arm/mach-rockchip/rk3399/
A Drk3399.c72 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); in rockchip_stimer_init()
77 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L); in rockchip_stimer_init()
78 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H); in rockchip_stimer_init()
79 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L); in rockchip_stimer_init()
80 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H); in rockchip_stimer_init()
81 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \ in rockchip_stimer_init()
/u-boot/include/configs/
A Drk3368_common.h21 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020 macro
A Drk3128_common.h15 #define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 macro
A Drk3036_common.h14 #define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 macro
A Drk322x_common.h15 #define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020 macro
A Drk3328_common.h13 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020 macro
A Drk3288_common.h17 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 macro
A Dpx30_common.h16 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020 macro
A Drk3308_common.h25 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0 macro
A Drk3399_common.h15 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0 macro
/u-boot/scripts/
A Dconfig_whitelist.txt1371 CONFIG_ROCKCHIP_STIMER_BASE

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