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Searched refs:CONFIG_SYS_CLK (Results 1 – 25 of 27) sorted by relevance

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/u-boot/include/configs/
A Damcore.h37 #define CONFIG_SYS_CLK 45000000 macro
38 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
A DM5235EVB.h88 #define CONFIG_SYS_CLK 75000000 macro
89 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
A DM53017EVB.h91 #define CONFIG_SYS_CLK 80000000 macro
92 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
A DM5373EVB.h87 #define CONFIG_SYS_CLK 80000000 macro
88 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
A DM5329EVB.h85 #define CONFIG_SYS_CLK 80000000 macro
86 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
A Dastro_mcf5373l.h73 #define CONFIG_SYS_CLK 80000000 macro
74 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3)
A DM5253DEMO.h89 # define CONFIG_SYS_CLK 140000000 macro
92 # define CONFIG_SYS_CLK 70000000 macro
A DM5485EVB.h106 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK macro
107 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
A DM5475EVB.h118 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK macro
119 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
A DM5249EVB.h42 #define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ macro
A DM5208EVBE.h76 #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ macro
A DM5275EVB.h93 #define CONFIG_SYS_CLK 150000000 macro
A DM5282EVB.h77 #define CONFIG_SYS_CLK 64000000 macro
A DM5272C3.h79 #define CONFIG_SYS_CLK 66000000 macro
A Dcobra5272.h32 #define CONFIG_SYS_CLK 66000000 macro
A Deb_cpu5282.h58 #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ macro
/u-boot/arch/m68k/cpu/mcf52x2/
A Dcpu.c135 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK)); in print_cpuinfo()
139 pin, prn, strmhz(buf, CONFIG_SYS_CLK)); in print_cpuinfo()
287 strmhz(buf, CONFIG_SYS_CLK)); in print_cpuinfo()
373 strmhz(buf, CONFIG_SYS_CLK)); in print_cpuinfo()
397 strmhz(buf, CONFIG_SYS_CLK)); in print_cpuinfo()
A Dspeed.c71 gd->cpu_clk = CONFIG_SYS_CLK; in get_clocks()
/u-boot/arch/m68k/cpu/mcf530x/
A Dspeed.c19 gd->bus_clk = CONFIG_SYS_CLK; in get_clocks()
/u-boot/board/freescale/m5253demo/
A Dm5253demo.c39 RC = (CONFIG_SYS_CLK / 1000000) >> 1; in dram_init()
121 period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ in ide_set_reset()
/u-boot/arch/m68k/cpu/mcf547x_8x/
A Dspeed.c25 gd->bus_clk = CONFIG_SYS_CLK; in get_clocks()
/u-boot/arch/m68k/cpu/mcf523x/
A Dspeed.c32 gd->bus_clk = CONFIG_SYS_CLK; in get_clocks()
A Dcpu.c95 wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT); in watchdog_init()
/u-boot/arch/m68k/cpu/mcf532x/
A Dcpu.c134 wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); in watchdog_init()
/u-boot/board/BuS/eb_cpu5282/
A Deb_cpu5282.c46 MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4); in dram_init()

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