CONFIG_SYS_DDR_TIMING_1 (reference) in projects: u-boot

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Searched refs:CONFIG_SYS_DDR_TIMING_1 (Results 1 – 25 of 46) sorted by relevance

/u-boot/include/configs/
A D	MPC8349EMDS.h	`78 #define CONFIG_SYS_DDR_TIMING_1 0x38357322 macro 91 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 macro`
A D	MPC8349EMDS_SDRAM.h	`78 #define CONFIG_SYS_DDR_TIMING_1 0x38357322 macro 91 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 macro`
A D	socrates.h	`81 #define CONFIG_SYS_DDR_TIMING_1 0x3935D322 macro`
A D	mpc8308_p1m.h	`76 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ macro`
A D	sbc8349.h	`67 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 macro`
A D	ve8313.h	`61 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ macro`
A D	MPC8323ERDB.h	`51 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ macro`
A D	MPC8308RDB.h	`72 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ macro`
A D	MPC832XEMDS.h	`49 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ macro`
A D	MPC8540ADS.h	`82 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 macro`
A D	ids8313.h	`69 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) \|\ macro`
A D	MPC8313ERDB_NOR.h	`82 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ macro`
A D	MPC8313ERDB_NAND.h	`111 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ macro`
/u-boot/include/configs/km/
A D	km-mpc8360.h	`49 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) \| \ macro`
A D	km-mpc832x.h	`52 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) \| \ macro`
A D	km-mpc8309.h	`103 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) \| \ macro`
/u-boot/board/socrates/
A D	sdram.c	`40 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()`
/u-boot/board/freescale/mpc8349emds/
A D	mpc8349emds.c	`109 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram() 134 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()`
/u-boot/board/mpc8308_p1m/
A D	sdram.c	`46 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()`
/u-boot/board/freescale/mpc8308rdb/
A D	sdram.c	`50 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()`
/u-boot/board/gdsys/mpc8308/
A D	sdram.c	`53 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()`
/u-boot/board/freescale/mpc8315erdb/
A D	sdram.c	`68 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()`
/u-boot/board/freescale/mpc8313erdb/
A D	sdram.c	`77 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()`
/u-boot/board/freescale/mpc832xemds/
A D	mpc832xemds.c	`141 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()`
/u-boot/board/Arcturus/ucp1020/
A D	ddr.c	`93 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, in fixed_sdram()`

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