Searched refs:CONFIG_SYS_DDR_TIMING_5 (Results 1 – 8 of 8) sorted by relevance
| /u-boot/board/freescale/corenet_ds/ |
| A D | p4080ds_ddr.c | 67 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 macro
102 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
134 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
166 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
198 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
230 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
262 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
294 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
326 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /u-boot/board/freescale/p1010rdb/ |
| A D | ddr.c | 41 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
68 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /u-boot/board/Arcturus/ucp1020/ |
| A D | ddr.c | 106 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, in fixed_sdram()
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| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| A D | ddr.c | 235 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, in fixed_sdram()
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| /u-boot/include/configs/ |
| A D | UCP1020.h | 214 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
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| A D | P1010RDB.h | 230 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
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| A D | p1_p2_rdb_pc.h | 221 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
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| /u-boot/scripts/ |
| A D | config_whitelist.txt | 2052 CONFIG_SYS_DDR_TIMING_5
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