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Searched refs:CONFIG_SYS_FLASH_BASE_PHYS (Results 1 – 25 of 61) sorted by relevance

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/u-boot/include/configs/
A DMPC8548CDS.h135 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull macro
137 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE macro
141 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
143 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
149 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
A Dcorenet_ds.h137 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull macro
139 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE macro
143 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
149 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
227 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_…
A Dls1021aqds.h110 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE macro
113 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
118 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
150 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
151 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
A Dls1046aqds.h88 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE macro
119 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
124 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
152 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
153 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
A DP2041RDB.h127 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull macro
129 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE macro
133 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
216 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
A DT4240RDB.h111 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) macro
299 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
305 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
334 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
335 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
A Dls1021atwr.h113 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE macro
116 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
147 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
A Dls1043aqds.h102 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
107 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
134 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
135 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
A DT208xQDS.h166 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) macro
168 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
174 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
203 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
204 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
A DUCP1020.h244 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE macro
246 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
251 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
A DP1010RDB.h284 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) macro
286 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE macro
289 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
306 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
A DT102xRDB.h204 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) macro
206 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE macro
210 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
244 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
A Dp1_p2_rdb_pc.h262 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) macro
264 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE macro
267 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
272 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
/u-boot/arch/powerpc/cpu/mpc8xxx/
A Dpamu_table.c24 #ifdef CONFIG_SYS_FLASH_BASE_PHYS in construct_pamu_addr_table()
26 (uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS); in construct_pamu_addr_table()
/u-boot/board/freescale/p1010rdb/
A Dtlb.c44 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
49 CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
A Dlaw.c11 SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
/u-boot/board/Arcturus/ucp1020/
A Dlaw.c18 SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
/u-boot/board/freescale/p1_p2_rdb_pc/
A Dlaw.c16 SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
/u-boot/board/keymile/kmcent2/
A Dlaw.c16 SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
/u-boot/board/freescale/t208xqds/
A Dlaw.c14 SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
/u-boot/board/freescale/t208xrdb/
A Dlaw.c14 SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
/u-boot/board/freescale/t4rdb/
A Dlaw.c11 SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
/u-boot/board/freescale/t102xrdb/
A Dlaw.c12 SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
/u-boot/board/freescale/t104xrdb/
A Dlaw.c12 SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
/u-boot/board/freescale/common/p_corenet/
A Dlaw.c14 SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),

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