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Searched refs:CONFIG_SYS_I2C_RTC_ADDR (Results 1 – 25 of 55) sorted by relevance

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/u-boot/drivers/rtc/
A Dm41t11.c78 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT); in rtc_get()
96 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, &cent, M41T11_YEAR_SIZE); in rtc_get()
104 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, &cent, M41T11_YEAR_SIZE); in rtc_get()
149 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, &cent, M41T11_YEAR_SIZE); in rtc_set()
152 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT); in rtc_set()
161 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, 1); in rtc_reset()
163 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, RTC_REG_CNT); in rtc_reset()
165 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1); in rtc_reset()
167 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1); in rtc_reset()
A Dds1374.c32 #ifndef CONFIG_SYS_I2C_RTC_ADDR
33 # define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
197 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); in rtc_read()
203 val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg); in rtc_write()
204 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write()
206 val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val; in rtc_write()
207 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write()
213 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write_raw()
A Drs5c372.c42 #ifndef CONFIG_SYS_I2C_RTC_ADDR
43 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 macro
66 ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, len); in rs5c372_readram()
106 ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1); in rs5c372_enable()
207 ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1); in rtc_set()
236 ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8); in rtc_set()
A Dmax6900.c19 #ifndef CONFIG_SYS_I2C_RTC_ADDR
20 #define CONFIG_SYS_I2C_RTC_ADDR 0x50 macro
27 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); in rtc_read()
32 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write()
A Dm41t60.c64 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { in rtc_dump()
93 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { in rtc_validate()
104 if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC, 1, data, 1)) { in rtc_validate()
140 if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { in rtc_validate()
191 if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, RTC_REG_CNT)) { in rtc_set()
234 if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CTRL, 1, data + RTC_CTRL, 1)) { in rtc_reset()
A Drx8025.c27 #ifndef CONFIG_SYS_I2C_RTC_ADDR
28 # define CONFIG_SYS_I2C_RTC_ADDR 0x32 macro
283 .chip = CONFIG_SYS_I2C_RTC_ADDR,
292 .chip = CONFIG_SYS_I2C_RTC_ADDR,
301 .chip = CONFIG_SYS_I2C_RTC_ADDR,
A Drx8010sj.c36 #ifndef CONFIG_SYS_I2C_RTC_ADDR
37 # define CONFIG_SYS_I2C_RTC_ADDR 0x32 macro
316 .chip = CONFIG_SYS_I2C_RTC_ADDR, in rtc_get()
325 .chip = CONFIG_SYS_I2C_RTC_ADDR, in rtc_set()
334 .chip = CONFIG_SYS_I2C_RTC_ADDR, in rtc_reset()
343 .chip = CONFIG_SYS_I2C_RTC_ADDR, in rtc_init()
A Dm41t62.c322 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); in rtc_get()
332 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); in rtc_set()
335 if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, in rtc_set()
352 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); in rtc_reset()
354 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); in rtc_reset()
A Dx1205.c80 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1); in rtc_write()
92 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); in rtc_get()
A Dds1307.c67 #ifndef CONFIG_SYS_I2C_RTC_ADDR
68 # define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
199 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); in rtc_read()
205 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write()
A Dpcf8563.c114 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); in rtc_read()
119 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write()
/u-boot/drivers/bootcount/
A Dbootcount_i2c.c20 ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, in bootcount_store()
31 ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, in bootcount_load()
/u-boot/board/freescale/mpc8349itx/
A Dmpc8349itx.c266 #ifdef CONFIG_SYS_I2C_RTC_ADDR in misc_init_r()
320 #ifdef CONFIG_SYS_I2C_RTC_ADDR in misc_init_r()
323 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) in misc_init_r()
367 (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, in misc_init_r()
/u-boot/include/configs/
A Dtqma6_wru4.h23 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
A Dsocfpga_arria5_secu1.h28 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
A Dxpedite520x.h61 CONFIG_SYS_I2C_RTC_ADDR}
186 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
A Dxpedite550x.h78 CONFIG_SYS_I2C_RTC_ADDR}
219 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
A Dls1012aqds.h53 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ macro
A Dethernut5.h94 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 macro
A Dls1046afrwy.h93 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ macro
A Dm53menlo.h103 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
A DTQM834x.h125 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ macro
A Dx600.h77 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
A Dls2080ardb.h282 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 macro
285 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
A Dlx2160a_common.h110 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ macro

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