Home
last modified time | relevance | path

Searched refs:CONFIG_SYS_INIT_L3_ADDR (Results 1 – 23 of 23) sorted by relevance

/u-boot/arch/powerpc/include/asm/
A Dfsl_secure_boot.h40 #undef CONFIG_SYS_INIT_L3_ADDR
41 #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 macro
45 #undef CONFIG_SYS_INIT_L3_ADDR
47 #define CONFIG_SYS_INIT_L3_ADDR \ macro
51 #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 macro
/u-boot/board/freescale/t104xrdb/
A Dtlb.c30 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
36 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
48 CONFIG_SYS_INIT_L3_ADDR,
/u-boot/board/freescale/common/p_corenet/
A Dtlb.c44 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
51 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
62 CONFIG_SYS_INIT_L3_ADDR & 0xfff00000,
/u-boot/board/varisys/cyrus/
A Dtlb.c31 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
36 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
/u-boot/board/freescale/t102xrdb/
A Dtlb.c30 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
35 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
/u-boot/board/freescale/t4rdb/
A Dtlb.c30 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
33 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
/u-boot/board/freescale/t208xqds/
A Dtlb.c33 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
38 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
/u-boot/board/freescale/t208xrdb/
A Dtlb.c33 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
38 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
/u-boot/board/keymile/kmp204x/
A Dtlb.c37 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
/u-boot/include/configs/
A Dt4qds.h46 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 macro
48 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
A Dcyrus.h76 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE macro
80 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
83 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
A DP2041RDB.h75 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE macro
80 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
83 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
A Dcorenet_ds.h89 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE macro
93 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
96 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
A Dkmp204x.h72 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE macro
76 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
A DT4240RDB.h84 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 macro
86 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
A DT208xRDB.h110 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 macro
112 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
A DT208xQDS.h128 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 macro
130 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
A DT102xRDB.h159 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 macro
161 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
A Dkmcent2.h168 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 macro
A DT104xRDB.h187 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 macro
/u-boot/arch/powerpc/cpu/mpc85xx/
A Dcpu_init.c230 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); in disable_cpc_sram()
A Dstart.S1058 CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
/u-boot/scripts/
A Dconfig_whitelist.txt2747 CONFIG_SYS_INIT_L3_ADDR

Completed in 62 milliseconds