| /u-boot/board/varisys/cyrus/ |
| A D | tlb.c | 59 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
65 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
70 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
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| /u-boot/board/freescale/t4rdb/ |
| A D | tlb.c | 55 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
61 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
66 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
|
| /u-boot/board/freescale/common/p_corenet/ |
| A D | tlb.c | 94 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
100 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
105 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
|
| /u-boot/board/gdsys/p1022/ |
| A D | tlb.c | 52 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
56 CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
|
| /u-boot/board/xes/xpedite537x/ |
| A D | tlb.c | 54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
|
| /u-boot/board/xes/xpedite550x/ |
| A D | tlb.c | 54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
|
| /u-boot/include/configs/ |
| A D | xpedite517x.h | 277 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS macro
341 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
345 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
349 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
|
| A D | controlcenterd.h | 205 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull macro
208 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 macro
|
| A D | sbc8641d.h | 254 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS macro
337 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
340 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
|
| A D | MPC8548CDS.h | 342 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull macro
344 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 macro
|
| A D | cyrus.h | 233 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull macro
236 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 macro
|
| A D | mpc8308_p1m.h | 187 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 macro
|
| A D | t4qds.h | 145 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull macro
|
| A D | MPC8308RDB.h | 208 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 macro
|
| /u-boot/board/mpc8308_p1m/ |
| A D | mpc8308_p1m.c | 31 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
|
| /u-boot/board/freescale/p1010rdb/ |
| A D | tlb.c | 55 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
| /u-boot/board/Arcturus/ucp1020/ |
| A D | tlb.c | 52 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
| /u-boot/board/keymile/kmp204x/ |
| A D | tlb.c | 50 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
| /u-boot/board/keymile/kmcent2/ |
| A D | tlb.c | 49 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| A D | tlb.c | 48 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
| /u-boot/board/freescale/mpc837xerdb/ |
| A D | pci.c | 37 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
|
| /u-boot/board/freescale/t102xrdb/ |
| A D | tlb.c | 57 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
| /u-boot/board/freescale/t104xrdb/ |
| A D | tlb.c | 70 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
| /u-boot/board/freescale/mpc8308rdb/ |
| A D | mpc8308rdb.c | 95 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
|
| /u-boot/board/freescale/mpc837xemds/ |
| A D | pci.c | 43 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
|