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Searched refs:CONFIG_SYS_SDRAM_BASE (Results 1 – 25 of 622) sorted by relevance

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/u-boot/include/configs/
A Dexynos7420-common.h45 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
47 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
49 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
51 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
53 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
55 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
57 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
59 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
61 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
A Dexynos5-common.h52 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
56 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
58 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
60 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
62 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
64 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
66 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
68 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
70 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
A Dsmdkv310.h23 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
37 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
41 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
43 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
45 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
47 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
A Dat91rm9200ek.h57 #define CONFIG_SYS_SDRAM_BASE 0x20000000 macro
81 #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
82 #define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80)
147 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
159 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
A Dsmdkc100.h28 #define CONFIG_SYS_SDRAM_BASE 0x30000000 macro
109 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
112 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
130 #define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
A Dboston.h27 # define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 macro
29 # define CONFIG_SYS_SDRAM_BASE 0x80000000 macro
36 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
A Demsdp.h13 #define CONFIG_SYS_SDRAM_BASE 0x10000000 macro
16 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M)
19 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
A Dgrpeach.h19 #define CONFIG_SYS_SDRAM_BASE 0x20000000 macro
22 (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
24 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
A Dmicrochip_mpfs_icicle.h12 #define CONFIG_SYS_SDRAM_BASE 0x80000000 macro
13 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
15 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
A Dhikey960.h21 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 macro
25 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
27 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
A Dbcm_ep_board.h20 #ifndef CONFIG_SYS_SDRAM_BASE
21 #error CONFIG_SYS_SDRAM_BASE must be defined!
30 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
A Ddragonboard820c.h22 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 macro
23 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
24 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
A Dorigen.h18 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
19 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
23 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
A Dtrats.h25 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
26 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
30 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
148 #define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100
A Dmalta.h33 # define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 macro
35 # define CONFIG_SYS_SDRAM_BASE 0x80000000 macro
41 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000)
A Docteontx2_common.h16 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_TEXT_BASE macro
19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0)
24 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
A Dthunderx_88xx.h20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
23 #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
50 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 macro
A Dqemu-arm.h13 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
16 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
17 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
A Diot_devkit.h55 #define CONFIG_SYS_SDRAM_BASE DCCM_BASE macro
58 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
70 CONFIG_SYS_SDRAM_BASE) - \
A Dhikey.h32 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 macro
36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
38 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
A Docteontx_common.h17 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_TEXT_BASE macro
20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0)
25 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
/u-boot/board/freescale/m5275evb/
A Dm5275evb.c38 out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE); in dram_init()
52 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
58 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
62 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
69 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
74 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
75 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
79 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
/u-boot/arch/arm/mach-sunxi/
A Ddram_helpers.c33 writel(0, CONFIG_SYS_SDRAM_BASE); in mctl_mem_matches()
34 writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); in mctl_mem_matches()
37 return readl(CONFIG_SYS_SDRAM_BASE) == in mctl_mem_matches()
38 readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); in mctl_mem_matches()
/u-boot/arch/arm/mach-at91/arm926ejs/
A Dlowlevel_init.S204 .word CONFIG_SYS_SDRAM_BASE
208 .word CONFIG_SYS_SDRAM_BASE
210 .word CONFIG_SYS_SDRAM_BASE
212 .word CONFIG_SYS_SDRAM_BASE
214 .word CONFIG_SYS_SDRAM_BASE
216 .word CONFIG_SYS_SDRAM_BASE
218 .word CONFIG_SYS_SDRAM_BASE
220 .word CONFIG_SYS_SDRAM_BASE
222 .word CONFIG_SYS_SDRAM_BASE
226 .word CONFIG_SYS_SDRAM_BASE
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/u-boot/drivers/ram/rockchip/
A Dsdram_common.c223 writel(0, CONFIG_SYS_SDRAM_BASE); in sdram_detect_col()
228 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) in sdram_detect_col()
250 writel(0, CONFIG_SYS_SDRAM_BASE); in sdram_detect_bank()
253 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) in sdram_detect_bank()
273 writel(0, CONFIG_SYS_SDRAM_BASE); in sdram_detect_bg()
276 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) in sdram_detect_bg()
340 writel(0, CONFIG_SYS_SDRAM_BASE); in sdram_detect_row()
345 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) in sdram_detect_row()
366 test_addr = CONFIG_SYS_SDRAM_BASE; in sdram_detect_row_3_4()
427 writel(0, CONFIG_SYS_SDRAM_BASE + cs0_cap); in sdram_detect_cs1_row()
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