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Searched refs:CORE_L4_DIV (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-omap2/omap3/
A Dclock.c173 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_34xx()
220 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_34xx()
423 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_36xx()
470 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_36xx()
/u-boot/arch/arm/include/asm/arch-omap3/
A Dclocks_omap3.h25 #define CORE_L4_DIV 2 /* 83MHz : L4 */ macro

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