Searched refs:CP (Results 1 – 25 of 31) sorted by relevance

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/u-boot/board/lg/sniper/
A D	sniper.h	15 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* sdrc_d0 */\ 16 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* sdrc_d1 */\ 17 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* sdrc_d2 */\ 18 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* sdrc_d3 */\ 19 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* sdrc_d4 */\ 20 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* sdrc_d5 */\ 78 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTD | DIS | M7)) \ 87 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M7)) \ 88 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M7)) \ 89 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M7)) \ [all …]
/u-boot/board/technexion/tao3530/
A D	tao3530.h	31 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ 32 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ 33 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ 34 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ 35 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ 36 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ 37 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ 38 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ 39 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ 40 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ [all …]
A D	tao3530.c	39 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); in tao3530_revision() 46 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M4)); in tao3530_revision() 63 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M0)); in tao3530_revision() 66 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); in tao3530_revision()
/u-boot/board/ti/am3517crane/
A D	am3517crane.h	67 MUX_VAL(CP(SDRC_CKE0), (M0))\ 75 MUX_VAL(CP(SDRC_CKE0), (M0))\ 76 MUX_VAL(CP(SDRC_CKE1), (M0))\ 82 MUX_VAL(CP(GPMC_A1), (M7))\ 87 MUX_VAL(CP(GPMC_A6), (M7))\ 90 MUX_VAL(CP(GPMC_A9), (M7))\ 91 MUX_VAL(CP(GPMC_A10), (M7))\ 110 MUX_VAL(CP(GPMC_NCS2), (M7))\ 115 MUX_VAL(CP(GPMC_NCS7), (M7))\ 202 MUX_VAL(CP(UART1_TX), (M7))\ [all …]
/u-boot/board/ti/evm/
A D	evm.h	50 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ 51 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ 52 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ 53 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ 54 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ 55 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ 56 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ 57 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ 58 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ 59 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ [all …]
/u-boot/board/logicpd/am3517evm/
A D	am3517evm.h	34 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ 35 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ 36 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ 37 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ 75 MUX_VAL(CP(SDRC_CKE0), (M0)) \ 76 MUX_VAL(CP(SDRC_CKE1), (M0)) \ 284 MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ 288 MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ 289 MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ 290 MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ [all …]
/u-boot/board/corscience/tricorder/
A D	tricorder.h	31 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ 32 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ 33 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ 34 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ 35 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ 36 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ 37 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ 38 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ 39 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ 40 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ [all …]
/u-boot/board/timll/devkit8000/
A D	devkit8000.h	34 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ 35 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ 36 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ 37 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ 38 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ 39 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ 40 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ 41 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ 42 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ 43 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ [all …]
/u-boot/board/logicpd/omap3som/
A D	omap3logic.h	48 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ in set_muxconf_regs() 49 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ in set_muxconf_regs() 50 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ in set_muxconf_regs() 51 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ in set_muxconf_regs() 52 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ in set_muxconf_regs() 53 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ in set_muxconf_regs() 54 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ in set_muxconf_regs() 55 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ in set_muxconf_regs() 56 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ in set_muxconf_regs() 57 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ in set_muxconf_regs() [all …]
/u-boot/board/ti/beagle/
A D	beagle.h	40 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ 41 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ 42 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ 43 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ 44 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ 45 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ 46 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ 47 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ 48 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ 49 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ [all …]
/u-boot/board/isee/igep00x0/
A D	igep00x0.h	20 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ 21 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ 22 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ 23 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ 24 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ 25 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ 26 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ 27 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ 28 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ 29 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ [all …]
/u-boot/doc/mvebu/
A D	armada-8k-memory.txt	7 a single CP configuration, then all secondary-CP mappings are invalid. 25 0xF6000000 0xF6FFFFFF CP-0 / PCIe#0 Memory space. 27 0xF7000000 0xF7FFFFFF CP-0 / PCIe#1 Memory space. 29 0xF8000000 0xF8FFFFFF CP-0 / PCIe#2 Memory space. 31 0xF9000000 0xF900FFFF CP-0 / PCIe#0 IO space. 33 0xF9010000 0xF901FFFF CP-0 / PCIe#1 IO space. 35 0xF9020000 0xF902FFFF CP-0 / PCIe#2 IO space. 39 0xFA000000 0xFAFFFFFF CP-1 / PCIe#0 Memory space. 45 0xFD000000 0xFD00FFFF CP-1 / PCIe#0 IO space. 47 0xFD010000 0xFD01FFFF CP-1 / PCIe#1 IO space. [all …]
/u-boot/include/linux/
A D	asn1_ber_bytecode.h	84 #define _tag(CLASS, CP, TAG) ((ASN1_##CLASS << 6) | (ASN1_##CP << 5) | ASN1_##TAG) argument 85 #define _tagn(CLASS, CP, TAG) ((ASN1_##CLASS << 6) | (ASN1_##CP << 5) | TAG) argument
/u-boot/include/
A D	i8042.h	58 #define CP 5 /* capslock index */ macro
/u-boot/configs/
A D	integratorcp_cm1136_defconfig	17 CONFIG_SYS_PROMPT="Integrator-CP # "
A D	integratorcp_cm920t_defconfig	17 CONFIG_SYS_PROMPT="Integrator-CP # "
A D	integratorcp_cm926ejs_defconfig	17 CONFIG_SYS_PROMPT="Integrator-CP # "
A D	integratorcp_cm946es_defconfig	17 CONFIG_SYS_PROMPT="Integrator-CP # "
/u-boot/arch/arm/dts/
A D	am57xx-beagle-x15-revc.dts	16 gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
A D	am57xx-beagle-x15-revb1.dts	16 gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
A D	am57xx-beagle-x15.dts	17 gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
A D	exynos4210-universal_c210.dts	217 cp32khz_reg: EN32KHz-CP { 218 regulator-name = "32KHz CP";
A D	omap5-uevm.dts	166 gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */
/u-boot/arch/arm/mach-integrator/
A D	Kconfig	12 bool "Support Integrator/CP platform"
/u-boot/arch/arm/include/asm/arch-omap3/
A D	mux.h	495 #define CP(x) (CONTROL_PADCONF_##x) macro

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Last Index update Sat Jun 03 09:59:21 CST 2023