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Searched refs:CPLD_WRITE (Results 1 – 19 of 19) sorted by relevance

/u-boot/board/freescale/ls1043ardb/
A Dcpld.c40 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_altbank()
41 CPLD_WRITE(cfg_rcw_src2, reg6); in cpld_set_altbank()
44 CPLD_WRITE(vbank, reg7); in cpld_set_altbank()
46 CPLD_WRITE(system_rst, 1); in cpld_set_altbank()
61 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_defbank()
64 CPLD_WRITE(vbank, 0); in cpld_set_defbank()
66 CPLD_WRITE(system_rst, 1); in cpld_set_defbank()
77 CPLD_WRITE(soft_mux_on, 1); in cpld_set_nand()
82 CPLD_WRITE(system_rst, 1); in cpld_set_nand()
93 CPLD_WRITE(soft_mux_on, 1); in cpld_set_sd()
[all …]
A Dcpld.h35 #define CPLD_WRITE(reg, value) \ macro
/u-boot/board/freescale/ls1046ardb/
A Dcpld.c40 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_altbank()
41 CPLD_WRITE(cfg_rcw_src2, reg6); in cpld_set_altbank()
44 CPLD_WRITE(vbank, reg7); in cpld_set_altbank()
46 CPLD_WRITE(system_rst, 1); in cpld_set_altbank()
61 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_defbank()
64 CPLD_WRITE(vbank, 0); in cpld_set_defbank()
66 CPLD_WRITE(system_rst, 1); in cpld_set_defbank()
77 CPLD_WRITE(soft_mux_on, 1); in cpld_set_sd()
82 CPLD_WRITE(system_rst, 1); in cpld_set_sd()
89 CPLD_WRITE(vdd_en, 1); in cpld_select_core_volt()
[all …]
A Dcpld.h40 #define CPLD_WRITE(reg, value) \ macro
/u-boot/board/freescale/t208xrdb/
A Dcpld.c32 CPLD_WRITE(flash_csr, reg); in cpld_set_altbank()
33 CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); in cpld_set_altbank()
42 CPLD_WRITE(flash_csr, reg); in cpld_set_defbank()
43 CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); in cpld_set_defbank()
A Dcpld.h30 #define CPLD_WRITE(reg, value) \ macro
A Dt208xrdb.c113 CPLD_WRITE(reset_ctl, reg); in misc_init_r()
/u-boot/board/freescale/p2041rdb/
A Dcpld.c42 CPLD_WRITE(system_rst, 1); in __cpld_reset()
53 CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE); in __cpld_set_altbank()
54 CPLD_WRITE(fbank_sel, 1); in __cpld_set_altbank()
55 CPLD_WRITE(system_rst, 1); in __cpld_set_altbank()
65 CPLD_WRITE(system_rst_default, 1); in __cpld_set_defbank()
129 CPLD_WRITE(serdes_mux, reg); in cpld_cmd()
A Dcpld.h54 #define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value) macro
A Dp2041rdb.c116 CPLD_WRITE(serdes_mux, mux); in board_config_lanes_mux()
/u-boot/board/freescale/t102xrdb/
A Dcpld.c38 CPLD_WRITE(flash_csr, reg); in cpld_set_altbank()
39 CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); in cpld_set_altbank()
51 CPLD_WRITE(flash_csr, reg); in cpld_set_defbank()
52 CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); in cpld_set_defbank()
A Dt102xrdb.c112 CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX); in board_mux_lane()
115 CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX); in board_mux_lane()
117 CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN); in board_mux_lane()
178 CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); in board_reset()
A Dcpld.h33 #define CPLD_WRITE(reg, value)\ macro
/u-boot/board/freescale/t104xrdb/
A Dcpld.c42 CPLD_WRITE(flash_ctl_status, reg); in cpld_set_altbank()
43 CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); in cpld_set_altbank()
55 CPLD_WRITE(flash_ctl_status, reg); in cpld_set_defbank()
56 CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); in cpld_set_defbank()
A Dt104xrdb.c105 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | in misc_init_r()
110 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | in misc_init_r()
115 CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) | in misc_init_r()
125 CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL & in misc_init_r()
A Dcpld.h42 #define CPLD_WRITE(reg, value)\ macro
A Ddiu.c73 CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP)); in platform_diu_init()
/u-boot/board/freescale/t4rdb/
A Dcpld.c51 CPLD_WRITE(vbank, altbank); in cpld_set_altbank()
53 CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); in cpld_set_altbank()
54 CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); in cpld_set_altbank()
71 CPLD_WRITE(global_reset, val); in cpld_set_defbank()
A Dcpld.h46 #define CPLD_WRITE(reg, value) \ macro

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