Searched refs:CPLL_HZ (Results 1 – 9 of 9) sorted by relevance
| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | cru_rk3328.h | 50 #define CPLL_HZ (594 * MHz) macro
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| A D | cru_rk3188.h | 13 #define CPLL_HZ (384 * 1000000) macro
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| A D | cru_rk3399.h | 72 #define CPLL_HZ (384*MHz) macro
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| A D | cru_rk3288.h | 15 #define CPLL_HZ (384 * 1000000) macro
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_rk3368.c | 44 #define CPLL_HZ (400 * 1000 * 1000) macro
59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
215 { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ }, in rk3368_mmc_find_best_rate_and_parent()
338 pll_rate = CPLL_HZ; in rk3368_gmac_set_clk()
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| A D | clk_rk3288.c | 149 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
326 pll_rate = CPLL_HZ; in rockchip_mac_set_clk()
849 div = CPLL_HZ / rate; in rk3288_clk_set_rate()
850 assert((div - 1 < 64) && (div * rate == CPLL_HZ)); in rk3288_clk_set_rate()
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| A D | clk_rk3328.c | 43 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
432 pll_rate = CPLL_HZ; in rk3328_gmac2io_set_clk()
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| A D | clk_rk3188.c | 87 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
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| A D | clk_rk3399.c | 58 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
702 div = CPLL_HZ / aclk_vop; in rk3399_vop_set_clk()
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