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Searched refs:CPM_CLKGR0 (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/mips/mach-jz47xx/jz4780/
A Dpll.c24 #define CPM_CLKGR0 0x20 macro
437 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_DDR0); in ddr_mux_select()
497 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_MAC); in jz4780_clk_ungate_ethernet()
498 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_NEMC); in jz4780_clk_ungate_ethernet()
521 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART0); in jz4780_clk_ungate_uart()
523 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART1); in jz4780_clk_ungate_uart()
525 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART2); in jz4780_clk_ungate_uart()
527 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART3); in jz4780_clk_ungate_uart()

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