| /u-boot/drivers/cpu/ |
| A D | Kconfig | 1 config CPU config
2 bool "Enable CPU drivers using Driver Model"
11 bool "Enable MPC83xx CPU driver"
12 depends on CPU
15 Support CPU cores for SoCs of the MPC83xx series.
18 bool "Enable RISC-V CPU driver"
19 depends on CPU && RISCV
21 Support CPU cores for RISC-V architecture.
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| /u-boot/doc/device-tree-bindings/cpu/ |
| A D | nios2.txt | 13 - reg: Contains CPU index.
14 - clock-frequency: Contains the clock frequency for CPU, in Hz.
19 - altr,reset-addr: Specifies CPU reset address
20 - altr,exception-addr: Specifies CPU exception address
23 - altr,has-initda: Specifies CPU support initda instruction, should be 1.
24 - altr,has-mmu: Specifies CPU support MMU support.
25 - altr,has-mul: Specifies CPU hardware multipy support.
26 - altr,has-div: Specifies CPU hardware divide support
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| /u-boot/arch/arm/cpu/armv7/ls102xa/ |
| A D | psci.S | 88 @ Get the real CPU number
105 @ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
113 @ r1 = target CPU
119 @ Clear and Get the correct CPU number
135 @ Detect target CPU state
142 @ Reset target CPU
158 @ Do reset on target CPU
164 @ Wait target CPU up
172 @ Release on target CPU
175 lsl r6, r6, r1 @ 32 bytes per CPU
[all …]
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| /u-boot/ |
| A D | config.mk | 24 CPU := $(CONFIG_SYS_CPU:"%"=%)
27 CPU := arm720t
42 CPUDIR=arch/$(ARCH)/cpu$(if $(CPU),/$(CPU),)
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| /u-boot/arch/x86/include/asm/acpi/ |
| A D | cpu.asl | 6 /* These come from the dynamically created CPU SSDT */
9 /* Notify OS to re-read CPU tables */
15 /* Notify OS to re-read CPU _PPC limit */
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| A D | lpc.asl | 107 IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
108 IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
109 IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
111 IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
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| /u-boot/arch/nds32/ |
| A D | Makefile | 3 head-y := arch/nds32/cpu/$(CPU)/start.o
5 libs-y += arch/nds32/cpu/$(CPU)/
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| /u-boot/board/google/chromebook_coral/ |
| A D | baseboard_dptf.asl | 37 /* CPU Throttle Effect on CPU */
40 /* CPU Effect on Temp Sensor 0 */
48 /* CPU Effect on Temp Sensor 1 */
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| /u-boot/arch/powerpc/ |
| A D | Makefile | 3 head-y := arch/powerpc/cpu/$(CPU)/start.o
6 libs-y += arch/powerpc/cpu/$(CPU)/
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| /u-boot/board/mikrotik/crs3xx-98dx3236/ |
| A D | README | 5 based on the Marvell Prestera 98DX3236 switch with an integrated CPU.
8 - Marvell Prestera 98DX3236 switch with an integrated ARMv7 CPU
18 - Gigabit Ethernet support (internal CPU <-> switch fabric connection)
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| /u-boot/doc/arch/ |
| A D | nds32.rst | 39 AndesCore CPU
41 Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
43 For details about N12 CPU family, please check below N1213 features.
44 N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
49 CPU Core
84 - Internal or external to CPU core.
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| /u-boot/board/qualcomm/dragonboard820c/ |
| A D | readme.txt | 375 CPU architecture: 8
376 CPU variant : 0x1
378 CPU revision : 2
384 CPU architecture: 8
385 CPU variant : 0x1
387 CPU revision : 2
393 CPU architecture: 8
394 CPU variant : 0x1
396 CPU revision : 2
402 CPU architecture: 8
[all …]
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| /u-boot/doc/device-tree-bindings/misc/misc/ |
| A D | gdsys,iocpu_fpga.txt | 1 gdsys IHS FPGA for CPU devices
3 The gdsys IHS FPGA is the main FPGA on gdsys CPU devices. This driver provides
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| /u-boot/arch/x86/include/asm/arch-quark/acpi/ |
| A D | lpc.asl | 111 IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
112 IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
113 IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
115 IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
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| /u-boot/arch/arm/mach-exynos/ |
| A D | Kconfig | 14 Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
33 Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
34 Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs
44 Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or
45 Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
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| /u-boot/arch/m68k/ |
| A D | Makefile | 3 head-y := arch/m68k/cpu/$(CPU)/start.o
5 libs-y += arch/m68k/cpu/$(CPU)/
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| /u-boot/arch/arm/mach-tegra/ |
| A D | psci.S | 30 @ converts CPU ID into FLOW_CTRL_CPUn_CSR offset
52 bl psci_get_cpu_id @ CPU ID => r0
72 bl psci_get_cpu_id @ CPU ID => r0
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| /u-boot/arch/arm/mach-tegra/tegra210/ |
| A D | Kconfig | 18 P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O
27 P2371-2180 (Jetson TX1 developer kit) is a P2180 CPU board married
42 P3450-0000 is a P3448 CPU board married to a P3449 I/O board.
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| /u-boot/board/efi/ |
| A D | Kconfig | 12 takes over once the RAM, video and CPU are fully running.
20 takes over once the RAM, video and CPU are fully running.
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| /u-boot/drivers/mailbox/ |
| A D | Kconfig | 9 CPU to another CPU, or sometimes to dedicated HW modules. They form
10 the basis of a variety of inter-process/inter-CPU communication
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| /u-boot/arch/sh/ |
| A D | Makefile | 5 libs-y += arch/sh/cpu/$(CPU)/
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| A D | config.mk | 7 ifeq ($(CPU),sh2)
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| /u-boot/doc/ |
| A D | I2C_Edge_Conditions | 5 and the CPU was reset. This may result in EEPROM data corruption.
11 4) The CPU is reset at this point.
13 Once the CPU reinitializes and the read is tried again:
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| /u-boot/doc/board/AndesTech/ |
| A D | adp-ag101p.rst | 6 ADP-AG101P is the SoC with AG101 hardcore CPU.
11 AG101P is the mainline SoC produced by Andes Technology using N1213 CPU core
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| /u-boot/arch/arm/mach-aspeed/ |
| A D | Kconfig | 22 The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU.
34 The Aspeed AST2600 is a ARM-based SoC with Cortex-A7 CPU.
|