Home
last modified time | relevance | path

Searched refs:CPU_CONFIGURATION_REG (Results 1 – 4 of 4) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_init.c383 reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET); in ddr3_init_main()
384 reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET); in ddr3_init_main()
386 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET); in ddr3_init_main()
388 reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET); in ddr3_init_main()
A Dddr3_axp.h30 #define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100)) macro
/u-boot/drivers/ddr/marvell/a38x/
A Dmv_ddr_plat.h74 #define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100)) macro
A Dmv_ddr_plat.c1219 reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET); in mv_ddr_pre_training_soc_config()
1220 reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET); in mv_ddr_pre_training_soc_config()
1223 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET); in mv_ddr_pre_training_soc_config()
1226 reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET); in mv_ddr_pre_training_soc_config()

Completed in 12 milliseconds