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Searched refs:CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca956x/
A Dclk.c117 #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB 24 macro
120 …(((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_…

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