Home
last modified time | relevance | path

Searched refs:CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca956x/
A Dclk.c179 #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL \ macro
272 writel(CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL | AHB_CLK_FROM_DDR | in qca956x_pll_init()

Completed in 3 milliseconds