Searched refs:CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca956x/
A D	clk.c	131 #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) \ macro 180 CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

Completed in 3 milliseconds

Last Index update Sat Jun 03 09:59:21 CST 2023