CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET (reference) in projects: u-boot

Searched refs:CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca956x/
A D	clk.c	`147 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) \ macro 251 CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1)); in qca956x_pll_init() 276 CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1) \| in qca956x_pll_init() 299 CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(0)); in qca956x_pll_init()`

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