Searched refs:CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca956x/
A D	clk.c	134 #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00 macro 136 (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK)

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