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Searched refs:CS1 (Results 1 – 25 of 39) sorted by relevance

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/u-boot/arch/arm/mach-omap2/omap3/
A Dsdrc.c174 write_sdrc_timings(CS1, sdrc_actim_base1, &timings); in do_sdrc_init()
185 if (cs == CS1) { in do_sdrc_init()
212 do_sdrc_init(CS1, NOT_EARLY); in dram_init()
213 size1 = get_sdr_cs_size(CS1); in dram_init()
225 size1 = get_sdr_cs_size(CS1); in dram_init_banksize()
229 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); in dram_init_banksize()
A Demif4.c140 size1 = get_sdr_cs_size(CS1); in dram_init()
151 size1 = get_sdr_cs_size(CS1); in dram_init_banksize()
155 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); in dram_init_banksize()
/u-boot/arch/mips/dts/
A Dmscc,ocelot_pcb.dtsi40 reg = <1>; /* CS1 */
/u-boot/doc/
A DREADME.fsl-ddr31 |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
32 |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
37 | |CS0 Only| | | {CS0+CS1} | |
40 | |CS0 Only| | | {CS0+CS1} | |
43 | |CS0 Only| | | {CS0+CS1} | |
46 | | | | | {CS0+CS1} | |
49 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
408 DDR Chip-Select Interleaving Mode: CS0+CS1
/u-boot/board/freescale/mpc8315erdb/
A DREADME38 0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K
42 is CS1.
/u-boot/board/Marvell/openrd/
A Dkwbimage.cfg128 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
134 # bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
136 # bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
/u-boot/board/freescale/mpc8313erdb/
A DREADME38 0xe280_0000 0xe280_7fff NAND FLASH (CS1) 32K
45 is CS1.
/u-boot/board/amazon/kc1/
A Dkc1.c60 if (cs == CS1) in emif_get_device_details()
/u-boot/doc/device-tree-bindings/mtd/
A Dstm32-fmc2-nand.txt11 Regions 5 to 7 contain the same areas for CS1.
/u-boot/board/d-link/dns325/
A Dkwbimage.cfg150 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
153 # bit3-2: 1, CS1 hit selected
164 # bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
/u-boot/board/cloudengines/pogo_e02/
A Dkwbimage.cfg138 # bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
140 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
/u-boot/board/iomega/iconnect/
A Dkwbimage.cfg134 # bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
136 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
/u-boot/board/raidsonic/ib62x0/
A Dkwbimage.cfg135 # bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
137 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
/u-boot/board/keymile/km83xx/
A DREADME.kmeter116 0x8000_0000 8 bit 256KB GPIO/PIGGY on CS1
/u-boot/board/freescale/mx51evk/
A Dimximage.cfg86 /* Init DRAM on CS1 */
/u-boot/arch/arm/dts/
A Darmada-370-xp.dtsi274 <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
292 <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
A Dk3-j7200-som-p0.dtsi68 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
/u-boot/arch/arm/mach-omap2/omap4/
A Dsdram_elpida.c171 && (cs == CS1)) { in emif_get_device_details_sdp()
/u-boot/board/freescale/mpc837xemds/
A DREADME54 0xf800_0000 0xf800_7fff BCSR on CS1 32K
/u-boot/board/cobra5272/bdm/
A Dcobra5272_uboot.gdb80 # CS1 -- external bus test
/u-boot/arch/arm/include/asm/arch-omap3/
A Dmem.h12 #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ macro
/u-boot/board/freescale/mpc832xemds/
A DREADME74 0xf800_0000 0xf800_7fff BCSR on CS1 32K
/u-boot/board/Marvell/sheevaplug/
A Dkwbimage.cfg128 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
/u-boot/board/Marvell/dreamplug/
A Dkwbimage.cfg129 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
/u-boot/board/Marvell/guruplug/
A Dkwbimage.cfg128 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1

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