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/u-boot/lib/
A Dsha1.c104 D = ctx->state[3]; in sha1_process()
110 P (A, B, C, D, E, W[0]); in sha1_process()
111 P (E, A, B, C, D, W[1]); in sha1_process()
112 P (D, E, A, B, C, W[2]); in sha1_process()
113 P (C, D, E, A, B, W[3]); in sha1_process()
114 P (B, C, D, E, A, W[4]); in sha1_process()
115 P (A, B, C, D, E, W[5]); in sha1_process()
116 P (E, A, B, C, D, W[6]); in sha1_process()
117 P (D, E, A, B, C, W[7]); in sha1_process()
118 P (C, D, E, A, B, W[8]); in sha1_process()
[all …]
A Dsha256.c62 uint32_t A, B, C, D, E, F, G, H; in sha256_process() local
108 D = ctx->state[3]; in sha256_process()
114 P(A, B, C, D, E, F, G, H, W[0], 0x428A2F98); in sha256_process()
115 P(H, A, B, C, D, E, F, G, W[1], 0x71374491); in sha256_process()
116 P(G, H, A, B, C, D, E, F, W[2], 0xB5C0FBCF); in sha256_process()
117 P(F, G, H, A, B, C, D, E, W[3], 0xE9B5DBA5); in sha256_process()
118 P(E, F, G, H, A, B, C, D, W[4], 0x3956C25B); in sha256_process()
119 P(D, E, F, G, H, A, B, C, W[5], 0x59F111F1); in sha256_process()
120 P(C, D, E, F, G, H, A, B, W[6], 0x923F82A4); in sha256_process()
121 P(B, C, D, E, F, G, H, A, W[7], 0xAB1C5ED5); in sha256_process()
[all …]
/u-boot/include/
A Dsignatures.h38 #define SIGNATURE_32(A, B, C, D) \ argument
39 (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16))
59 #define SIGNATURE_64(A, B, C, D, E, F, G, H) \ argument
60 (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))
/u-boot/scripts/kconfig/tests/rand_nested_choice/
A DKconfig17 config D config in choiceae7b601c0104""choiceae7b601c0204
18 bool "D"
20 if D
28 endif # D
/u-boot/arch/x86/include/asm/arch-baytrail/acpi/
A Dirqroute.h17 PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
20 PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
22 PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, B, C, D), \
23 PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
26 PCIE_BRIDGE_DEV(RP, PCIE_DEV, A, B, C, D)
A Dusb.asl18 /* Highest D state in S3 state */
21 /* Highest D state in S4 state */
/u-boot/arch/arm/dts/
A Dstm32mp15-pinctrl.dtsi311 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
314 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
315 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
316 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
317 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
355 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
357 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
358 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
359 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
360 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
[all …]
A Dstm32f746-disco-u-boot.dtsi123 pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
124 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
125 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
135 <STM32_PINMUX('D', 1, AF12)>, /* D3 */
136 <STM32_PINMUX('D', 0, AF12)>, /* D2 */
137 <STM32_PINMUX('D',15, AF12)>, /* D1 */
138 <STM32_PINMUX('D',14, AF12)>, /* D0 */
207 <STM32_PINMUX('D',11, AF9)>, /* BK1_IO0 */
208 <STM32_PINMUX('D',12, AF9)>, /* BK1_IO1 */
209 <STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
A Dstm32f429-disco-u-boot.dtsi140 pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
141 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
142 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
152 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
153 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
154 <STM32_PINMUX('D',15, AF12)>, /* D01 */
155 <STM32_PINMUX('D',14, AF12)>, /* D00 */
A Dstm32h7-u-boot.dtsi142 pinmux = <STM32_PINMUX('D', 0, AF12)>,
143 <STM32_PINMUX('D', 1, AF12)>,
144 <STM32_PINMUX('D', 8, AF12)>,
145 <STM32_PINMUX('D', 9, AF12)>,
146 <STM32_PINMUX('D',10, AF12)>,
147 <STM32_PINMUX('D',14, AF12)>,
148 <STM32_PINMUX('D',15, AF12)>,
A Dstm32f769-disco-u-boot.dtsi158 <STM32_PINMUX('D',10, AF12)>, /* D15 */
159 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
160 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
170 <STM32_PINMUX('D', 1, AF12)>, /* D3 */
171 <STM32_PINMUX('D', 0, AF12)>, /* D2 */
172 <STM32_PINMUX('D',15, AF12)>, /* D1 */
173 <STM32_PINMUX('D',14, AF12)>, /* D0 */
212 <STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
A Dstm32746g-eval-u-boot.dtsi108 <STM32_PINMUX('D',10, AF12)>, /* D15 */
109 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
110 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
120 <STM32_PINMUX('D', 1, AF12)>, /* D3 */
121 <STM32_PINMUX('D', 0, AF12)>, /* D2 */
122 <STM32_PINMUX('D',15, AF12)>, /* D1 */
123 <STM32_PINMUX('D',14, AF12)>, /* D0 */
A Dstm32429i-eval-u-boot.dtsi170 <STM32_PINMUX('D',10, AF12)>, /* D15 */
171 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
172 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
182 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
183 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
184 <STM32_PINMUX('D',15, AF12)>, /* D01 */
185 <STM32_PINMUX('D',14, AF12)>, /* D00 */
A Duniphier-ld6b.dtsi9 * LD6b consists of two silicon dies: D-chip and A-chip.
10 * The D-chip (digital chip) is the same as the PXs2 die.
A Dstm32f469-disco-u-boot.dtsi162 <STM32_PINMUX('D',10, AF12)>, /* D15 */
163 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
164 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
174 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
175 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
176 <STM32_PINMUX('D',15, AF12)>, /* D01 */
177 <STM32_PINMUX('D',14, AF12)>, /* D00 */
/u-boot/arch/x86/include/asm/arch-quark/acpi/
A Dirqroute.h11 PCI_DEV_PIRQ_ROUTE(QUARK_DEV_23, A, B, C, D)
14 PCIE_BRIDGE_DEV(RP, QUARK_DEV_23, A, B, C, D)
/u-boot/doc/chromium/devkeys/
A Dkernel.keyblock1 …@����@A-�mS�̧���"��:r�!�x�e ��=[^����gZF�,�*e��Y�p�N}�C.mr��q��:�D�у��ld��ۊ��փ��ꩁ�Z��…
3D�z�a��d�I����9����X�6���Lq�x���/�� M���?��Y��`���f��{�I�o{$�H��a��哇 :�T��)��ܯ��bĶ�/�T:…
5 گ��\F���l�N��k��K���6��Ց�~����ܾ���(/��kH�Q�m���li��(P~t��j �k��ޣ_#�*D��$63�~�������…
/u-boot/arch/arm/mach-snapdragon/
A Dclock-apq8016.c27 .D = SDCC_D(1),
34 .D = SDCC_D(2),
74 .D = BLSP1_UART2_APPS_D,
A Dclock-apq8096.c27 .D = SDCC2_D,
61 .D = BLSP2_UART2_APPS_D,
/u-boot/env/
A DKconfig442 "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
443 - "D:P": device D partition P. Error occurs if device D has no
445 - "D:0": device D.
446 - "D" or "D:": device D partition 1 if device D has partition
449 - "D:auto": first partition in device D with bootable flag set.
451 partition table then means device D.
478 "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
479 - "D:P": device D partition P. Error occurs if device D has no
481 - "D:0": device D.
482 - "D" or "D:": device D partition 1 if device D has partition
[all …]
/u-boot/doc/
A DREADME.arm-caches4 Disabling D-cache:
10 Enabling D-cache:
15 D-cache from this function. This function is called immediately
18 Guidelines for Working with D-cache:
47 - cleanup_before_linux() should flush the D-cache, invalidate I-cache, and
/u-boot/board/qualcomm/dragonboard820c/
A Dreadme.txt154 D - 30 - boot_flash_init, Delta
156 D - 30 - sbl1_ddr_set_default_params, Delta
165 D - 40016 - pm_device_init, Delta
167 D - 2928 - pm_driver_init, Delta
169 D - 91 - pm_sbl_chg_init, Delta
171 D - 0 - vsense_init, Delta
173 D - 396 - Pre_DDR_clock_init, Delta
180 D - 274 - clock_init, Delta
192 D - 457 - sbl1_efs_handle_cookies, Delta
198 D - 3233 - STI Image Loaded, Delta - (0 Bytes)
[all …]
/u-boot/drivers/clk/meson/
A DKconfig7 the S905, S905X/D and S912.
15 the A113X/D
/u-boot/drivers/bios_emulator/include/x86emu/
A Dregs.h98 i386_general_register A, B, C, D; member
131 #define R_DH gen.D.I8_reg.h_reg
132 #define R_DL gen.D.I8_reg.l_reg
138 #define R_DX gen.D.I16_reg.x_reg
144 #define R_EDX gen.D.I32_reg.e_reg
/u-boot/doc/board/st/
A Dstm32mp1.rst23 - 2D/3D image composition with GPU (only on STM32MP157)
33 - D : Cortex-A7 @ 800 MHz
575 $> dfu-util -d 0483:5720 -a 3 -D tf-a-stm32mp157c-ev1-trusted.stm32
576 $> dfu-util -d 0483:5720 -a 4 -D tf-a-stm32mp157c-ev1-trusted.stm32
577 $> dfu-util -d 0483:5720 -a 5 -D u-boot-stm32mp157c-ev1-trusted.img
585 $> dfu-util -d 0483:5720 -a 10 -D tf-a-stm32mp157c-ev1-trusted.stm32
586 $> dfu-util -d 0483:5720 -a 11 -D tf-a-stm32mp157c-ev1-trusted.stm32
587 $> dfu-util -d 0483:5720 -a 12 -D u-boot-stm32mp157c-ev1-trusted.img
604 $> dfu-util -d 0483:5720 -a 21 -D tf-a-stm32mp157c-ev1-trusted.stm32
605 $> dfu-util -d 0483:5720 -a 22 -D tf-a-stm32mp157c-ev1-trusted.stm32
[all …]

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