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Searched refs:DCACHELINE_SIZE (Results 1 – 1 of 1) sorted by relevance

/u-boot/drivers/usb/mtu3/
A Dmtu3_qmu.c37 #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
43 flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_flush_cache()
44 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_flush_cache()
51 invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), in mtu3_inval_cache()
52 ALIGN(addr + len, DCACHELINE_SIZE)); in mtu3_inval_cache()
108 gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); in mtu3_gpd_ring_alloc()

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