| /u-boot/drivers/ram/stm32mp1/ |
| A D | Kconfig | 3 bool "STM32MP1 DDR driver"
9 activate STM32MP1 DDR controller driver for STM32MP1 soc
12 in device tree (computed by DDR tuning tools)
15 bool "STM32MP1 DDR driver : interactive support"
19 used for DDR tuning tools
24 bool "STM32MP1 DDR driver : force interactive mode"
28 force interactive mode in STM32MP1 DDR controller driver
34 bool "STM32MP1 DDR driver : tests support"
39 STM32MP1 DDR controller driver: command test
42 bool "STM32MP1 DDR driver : support of tuning"
[all …]
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| /u-boot/board/Seagate/nas220/ |
| A D | kwbimage.cfg | 56 DATA 0xFFD0140C 0x00000819 # DDR Timing (High)
64 DATA 0xFFD01410 0x0000000d # DDR Address Control
83 DATA 0xFFD01418 0x00000000 # DDR Operation
84 # bit3-0: 0x0, DDR cmd
87 DATA 0xFFD0141C 0x00000632 # DDR Mode
98 DATA 0xFFD01420 0x00000040 # DDR Extended Mode
99 # bit0: 0, DDR DLL enabled
100 # bit1: 0, DDR drive strenght normal
101 # bit2: 0, DDR ODT control lsd (disabled)
103 # bit6: 1, DDR ODT control msb, (disabled)
[all …]
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| /u-boot/board/Marvell/sheevaplug/ |
| A D | kwbimage.cfg | 52 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
59 DATA 0xFFD01410 0x000000cc # DDR Address Control
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000C52 # DDR Mode
92 DATA 0xFFD01420 0x00000040 # DDR Extended Mode
93 # bit0: 0, DDR DLL enabled
94 # bit1: 0, DDR drive strenght normal
95 # bit2: 0, DDR ODT control lsd (disabled)
97 # bit6: 1, DDR ODT control msb, (disabled)
[all …]
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| /u-boot/board/Seagate/dockstar/ |
| A D | kwbimage.cfg | 55 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
62 DATA 0xFFD01410 0x0000000d # DDR Address Control
81 DATA 0xFFD01418 0x00000000 # DDR Operation
82 # bit3-0: 0x0, DDR cmd
85 DATA 0xFFD0141C 0x00000C52 # DDR Mode
95 DATA 0xFFD01420 0x00000040 # DDR Extended Mode
96 # bit0: 0, DDR DLL enabled
97 # bit1: 0, DDR drive strenght normal
98 # bit2: 0, DDR ODT control lsd (disabled)
100 # bit6: 1, DDR ODT control msb, (disabled)
[all …]
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| /u-boot/board/Seagate/goflexhome/ |
| A D | kwbimage.cfg | 58 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
65 DATA 0xFFD01410 0x0000000d # DDR Address Control
84 DATA 0xFFD01418 0x00000000 # DDR Operation
85 # bit3-0: 0x0, DDR cmd
88 DATA 0xFFD0141C 0x00000C52 # DDR Mode
98 DATA 0xFFD01420 0x00000040 # DDR Extended Mode
99 # bit0: 0, DDR DLL enabled
100 # bit1: 0, DDR drive strenght normal
101 # bit2: 0, DDR ODT control lsd (disabled)
103 # bit6: 1, DDR ODT control msb, (disabled)
[all …]
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| /u-boot/board/Synology/ds109/ |
| A D | kwbimage.cfg | 56 DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
63 DATA 0xFFD01410 0x0000000d # DDR Address Control
82 DATA 0xFFD01418 0x00000000 # DDR Operation
83 # bit3-0: 0x0, DDR cmd
86 DATA 0xFFD0141C 0x00000C52 # DDR Mode
96 DATA 0xFFD01420 0x00000042 # DDR Extended Mode
97 # bit0: 0, DDR DLL enabled
98 # bit1: 0, DDR drive strenght normal
99 # bit2: 0, DDR ODT control lsd (disabled)
101 # bit6: 1, DDR ODT control msb, (disabled)
[all …]
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| /u-boot/board/Marvell/dreamplug/ |
| A D | kwbimage.cfg | 53 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
60 DATA 0xFFD01410 0x000000cc # DDR Address Control
79 DATA 0xFFD01418 0x00000000 # DDR Operation
80 # bit3-0: 0x0, DDR cmd
83 DATA 0xFFD0141C 0x00000C52 # DDR Mode
93 DATA 0xFFD01420 0x00000040 # DDR Extended Mode
94 # bit0: 0, DDR DLL enabled
95 # bit1: 0, DDR drive strenght normal
96 # bit2: 0, DDR ODT control lsd (disabled)
98 # bit6: 1, DDR ODT control msb, (disabled)
[all …]
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| /u-boot/board/Marvell/guruplug/ |
| A D | kwbimage.cfg | 52 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
59 DATA 0xFFD01410 0x000000cc # DDR Address Control
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000C52 # DDR Mode
92 DATA 0xFFD01420 0x00000040 # DDR Extended Mode
93 # bit0: 0, DDR DLL enabled
94 # bit1: 0, DDR drive strenght normal
95 # bit2: 0, DDR ODT control lsd (disabled)
97 # bit6: 1, DDR ODT control msb, (disabled)
[all …]
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| /u-boot/board/Marvell/openrd/ |
| A D | kwbimage.cfg | 52 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
59 DATA 0xFFD01410 0x000000cc # DDR Address Control
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000C52 # DDR Mode
92 DATA 0xFFD01420 0x00000042 # DDR Extended Mode
93 # bit0: 0, DDR DLL enabled
94 # bit1: 1, DDR drive strength reduced
95 # bit2: 0, DDR ODT control lsd (disabled)
97 # bit6: 1, DDR ODT control msb, (disabled)
[all …]
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| /u-boot/board/LaCie/netspace_v2/ |
| A D | kwbimage-is2.cfg | 52 DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
59 DATA 0xFFD01410 0x00000008 # DDR Address Control
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000632 # DDR Mode
92 DATA 0xFFD01420 0x00000004 # DDR Extended Mode
93 # bit0: 0, DDR DLL enabled
94 # bit1: 1, DDR drive strenght reduced
95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
[all …]
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| A D | kwbimage-ns2l.cfg | 52 DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
59 DATA 0xFFD01410 0x0000DDDD # DDR Address Control
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000632 # DDR Mode
92 DATA 0xFFD01420 0x00000004 # DDR Extended Mode
93 # bit0: 0, DDR DLL enabled
94 # bit1: 1, DDR drive strenght reduced
95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
[all …]
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| A D | kwbimage.cfg | 52 DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
59 DATA 0xFFD01410 0x0000000C # DDR Address Control
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000632 # DDR Mode
92 DATA 0xFFD01420 0x00000004 # DDR Extended Mode
93 # bit0: 0, DDR DLL enabled
94 # bit1: 1, DDR drive strenght reduced
95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
[all …]
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| /u-boot/board/cloudengines/pogo_e02/ |
| A D | kwbimage.cfg | 56 DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
63 DATA 0xffd01410 0x000000cc # DDR Address Control
82 DATA 0xffd01418 0x00000000 # DDR Operation
83 # bit3-0: 0x0, DDR cmd
86 DATA 0xffd0141c 0x00000c52 # DDR Mode
96 DATA 0xffd01420 0x00000040 # DDR Extended Mode
97 # bit0: 0, DDR DLL enabled
98 # bit1: 0, DDR drive strenght normal
99 # bit2: 0, DDR ODT control lsd (disabled)
101 # bit6: 1, DDR ODT control msb, (disabled)
[all …]
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| /u-boot/board/iomega/iconnect/ |
| A D | kwbimage.cfg | 52 DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
59 DATA 0xffd01410 0x000000cc # DDR Address Control
78 DATA 0xffd01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xffd0141c 0x00000c52 # DDR Mode
92 DATA 0xffd01420 0x00000040 # DDR Extended Mode
93 # bit0: 0, DDR DLL enabled
94 # bit1: 0, DDR drive strenght normal
95 # bit2: 0, DDR ODT control lsd (disabled)
97 # bit6: 1, DDR ODT control msb, (disabled)
[all …]
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| /u-boot/board/raidsonic/ib62x0/ |
| A D | kwbimage.cfg | 53 DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
60 DATA 0xffd01410 0x0000000c # DDR Address Control
79 DATA 0xffd01418 0x00000000 # DDR Operation
80 # bit3-0: 0x0, DDR cmd
83 DATA 0xffd0141c 0x00000c52 # DDR Mode
93 DATA 0xffd01420 0x00000040 # DDR Extended Mode
94 # bit0: 0, DDR DLL enabled
95 # bit1: 0, DDR drive strenght normal
96 # bit2: 1, DDR ODT control lsd (disabled)
98 # bit6: 0, DDR ODT control msb, (disabled)
[all …]
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| /u-boot/board/LaCie/net2big_v2/ |
| A D | kwbimage.cfg | 52 DATA 0xFFD0140C 0x00000A32 # DDR Timing (High)
59 DATA 0xFFD01410 0x0000CCCC # DDR Address Control
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000662 # DDR Mode
92 DATA 0xFFD01420 0x00000044 # DDR Extended Mode
93 # bit0: 0, DDR DLL enabled
94 # bit1: 1, DDR drive strenght reduced
95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
[all …]
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| /u-boot/board/keymile/km_arm/ |
| A D | kwbimage.cfg | 73 DATA 0xFFD0140C 0x00000033 # DDR Timing (High)
80 DATA 0xFFD01410 0x0000000D # DDR Address Control
99 DATA 0xFFD01418 0x00000000 # DDR Operation
100 # bit3-0: 0x0, DDR cmd
103 DATA 0xFFD0141C 0x00000652 # DDR Mode
104 DATA 0xFFD01420 0x00000044 # DDR Extended Mode
105 # bit0: 0, DDR DLL enabled
106 # bit1: 0, DDR drive strenght normal
107 # bit2: 1, DDR ODT control lsd disabled
109 # bit6: 1, DDR ODT control msb, enabled
[all …]
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| A D | kwbimage-memphis.cfg | 76 DATA 0xFFD0140C 0x00000A3E # DDR Timing (High)
83 DATA 0xFFD01410 0x00000001 # DDR Address Control
102 DATA 0xFFD01418 0x00000000 # DDR Operation
103 # bit3-0: 0x0, DDR cmd
106 DATA 0xFFD0141C 0x00000652 # DDR Mode
107 DATA 0xFFD01420 0x00000006 # DDR Extended Mode
108 # bit0: 0, DDR DLL enabled
109 # bit1: 1, DDR drive strenght reduced
110 # bit2: 1, DDR ODT control lsd disabled
112 # bit6: 0, DDR ODT control msb disabled
[all …]
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| /u-boot/drivers/ram/ |
| A D | Kconfig | 18 setting up RAM (e.g. SDRAM / DDR) within SPL.
27 setting up RAM (e.g. SDRAM / DDR) within TPL.
41 Enable support for the internal DDR Memory Controller of the MPC83xx
50 K3 based AM654 devices has DDR memory subsystem that comprises
51 Synopys DDR controller, Synopsis DDR phy and wrapper logic to
52 intergrate these blocks into the device. This DDR subsystem
55 SDRAM devices connected to DDR subsystem.
61 The J721E DDR subsystem comprises DDR controller, DDR PHY and
62 wrapper logic to integrate these blocks in the device. The DDR
65 Enabling this config adds support for the DDR memory controller
|
| /u-boot/board/freescale/ls1012ardb/ |
| A D | Kconfig | 49 hex "PFE DDR physical base address"
53 hex "PFE DDR base address"
57 hex "PFE DDR base address"
61 hex "PFE DDR base address"
105 hex "PFE DDR physical base address"
109 hex "PFE DDR base address"
113 hex "PFE DDR base address"
117 hex "PFE DDR base address"
|
| /u-boot/board/freescale/ls1012aqds/ |
| A D | Kconfig | 55 hex "PFE DDR physical base address"
59 hex "PFE DDR base address"
63 hex "PFE DDR base address"
67 hex "PFE DDR base address"
71 hex "PFE DDR base address"
75 hex "PFE DDR base address"
|
| /u-boot/doc/ |
| A D | README.ramboot-ppc85xx | 4 RAMBOOT literally means boot from DDR. But since DDR is volatile memory some
5 pre-mechanism is required to load the DDR with the bootloader binary.
9 which can initialize the DDR and get the complete bootloader copied to DDR.
16 execute the bootloader from DDR.
23 the board.And then execute the bootloader from DDR.
29 In this case you can get your test bootloader binary into DDR via tftp
51 Preconfigure DDR/L2SRAM through JTAG interface.
52 - setup DDR controller registers.
53 - setup DDR LAWs
54 - setup DDR TLB
[all …]
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| /u-boot/board/freescale/t208xrdb/ |
| A D | t2080_nand_rcw.cfg | 5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
|
| A D | t2080_spi_rcw.cfg | 5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
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| A D | t2080_sd_rcw.cfg | 5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
|