| /u-boot/arch/arm/mach-keystone/include/mach/ |
| A D | clock-k2hk.h | 38 #define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
39 #define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
40 #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
41 #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
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| /u-boot/board/theobroma-systems/puma_rk3399/ |
| A D | Kconfig | 26 bool "DDR3-1333MHz"
29 bool "DDR3-1600MHz"
32 bool "DDR3-1866MHz"
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| /u-boot/drivers/ram/rockchip/ |
| A D | Kconfig | 26 bool "DDR3 support for Rockchip PX30"
29 This enables DDR4 sdram support instead of the default DDR3 support
36 This enables LPDDR2 sdram support instead of the default DDR3 support
43 This enables LPDDR3 sdram support instead of the default DDR3 support
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| A D | sdram_pctl_px30.c | 38 if (dramtype == DDR3 || dramtype == DDR4) { in pctl_write_mr()
173 if (cap_info->rank == 2 || dram_type == DDR3 || in pctl_remodify_sdram_params()
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| A D | sdram-px30-ddr3-detect-333.inc | 28 .dramtype = DDR3,
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| /u-boot/board/freescale/mx6memcal/ |
| A D | Kconfig | 88 Select the type of DDR (DDR3 or LPDDR2) used on your design
90 config DDR3 config in mx6memcal specifics""choicef565d0e00304
91 bool "DDR3"
93 Select this if your board design uses DDR3.
107 depends on DDR3
111 depends on DDR3
115 depends on DDR3
119 depends on DDR3
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| A D | README | 35 4. The type of DDR (DDR3 or LPDDR2). Note that LPDDR2 support
38 parts and four DDR3 and two LPDDR2 parts are currently defined
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| /u-boot/board/mikrotik/crs3xx-98dx3236/ |
| A D | README | 9 - 512 MB DDR3 RAM
22 binary.0 (DDR3 init phase) can be retrieved/extracted from the integrated bootloader on the SPI fla…
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| A D | kwbimage.cfg.in | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /u-boot/arch/mips/mach-mscc/ |
| A D | Kconfig | 65 bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)"
71 bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)"
74 bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)"
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | rockchip,rk3368-dmc.txt | 8 (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
19 the DDR3 device's speed-bin (as specified according to JESD-79)
51 Example (for DDR3-1600K and 800MHz)
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| /u-boot/arch/arm/mach-mediatek/ |
| A D | Kconfig | 29 including NEON and GPU, Mali-450 graphics, several DDR3 options,
42 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
62 chip and several DDR3 and DDR4 options.
71 chip and several DDR3 and DDR4 options.
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| /u-boot/board/alliedtelesis/x530/ |
| A D | kwbimage.cfg | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /u-boot/arch/arm/mach-mvebu/ |
| A D | kwbimage.cfg.in | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /u-boot/board/Marvell/db-xc3-24g4xg/ |
| A D | kwbimage.cfg.in | 11 # Binary Header (bin_hdr) with DDR3 training code
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| /u-boot/drivers/ddr/fsl/ |
| A D | Kconfig | 94 Enable Freescale DDR3 controller for PowerPC SoCs.
100 Enable Freescale DDR3 controller for ARM SoCs.
132 bool "Freescale DDR3 controller"
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | sdram.h | 11 DDR3 = 0x3, enumerator
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | Kconfig | 418 bool "DDR3 1333"
440 bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
445 which use a DDR3-1333 timing.
463 Set the dram type, 3: DDR3, 7: LPDDR3
478 (for DDR3-1600) are 312 to 792.
552 Select the timings of the DDR3 chips.
560 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
567 that down binning to DDR3-1066F is supported (because DDR3-1066F
568 uses a bit faster timings than DDR3-1333H).
571 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
[all …]
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| /u-boot/doc/device-tree-bindings/memory-controllers/ |
| A D | st,stm32mp1-ddr.txt | 1 ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
26 (DDR3/LPDDR2/LPDDR3)
104 - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
177 st,mem-name = "DDR3 2x4Gb 533MHz";
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| /u-boot/board/seco/mx6quq7/ |
| A D | mx6quq7-2g.cfg | 76 * DDR3 SETTINGS
115 * in DDR3, 64-bit mode, only MMDC0 is init
135 /* Initialize DDR3 on CS_0 and CS_1 */
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| /u-boot/arch/arm/mach-rockchip/ |
| A D | Kconfig | 21 including NEON and GPU, Mali-400 graphics, several DDR3 options
35 including NEON and GPU, Mali-400 graphics, several DDR3 options
45 including NEON and GPU, Mali-400 graphics, several DDR3 options
95 including NEON and GPU, Mali-400 graphics, several DDR3 options
128 video interfaces supporting HDMI and eDP, several DDR3 options
176 video interfaces supporting HDMI and eDP, several DDR3 options
198 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
256 video interfaces supporting HDMI and eDP, several DDR3 options
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| /u-boot/arch/arm/mach-rockchip/rv1108/ |
| A D | Kconfig | 16 * 128M DDR3
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| /u-boot/arch/arm/dts/ |
| A D | stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 8 * DDR type: DDR3 / DDR3L
18 #define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
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| A D | stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 8 * DDR type: DDR3 / DDR3L
18 #define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz"
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| A D | stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi | 9 * DDR type / Platform DDR3/3L
12 * datasheet 0 = W631GU6MB15I / DDR3-1333
|