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Searched refs:DDR3_MR1_DIC_7 (Results 1 – 2 of 2) sorted by relevance

/u-boot/board/imgtec/ci20/
A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/u-boot/arch/mips/mach-jz47xx/include/mach/
A Djz4780_dram.h392 #define DDR3_MR1_DIC_7 (0 << 5 | BIT(1)) macro

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