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Searched refs:DDRC_CTRL (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/mips/mach-jz47xx/jz4780/
A Dsdram.c215 writel(0xf << 20, ddr_ctl_regs + DDRC_CTRL); in sdram_init()
229 writel(0x0, ddr_ctl_regs + DDRC_CTRL); in sdram_init()
234 writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, ddr_ctl_regs + DDRC_CTRL); in sdram_init()
235 writel(0x0, ddr_ctl_regs + DDRC_CTRL); in sdram_init()
265 writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, ddr_ctl_regs + DDRC_CTRL); in sdram_init()
271 ddr_ctl_regs + DDRC_CTRL); in sdram_init()
/u-boot/arch/mips/mach-jz47xx/include/mach/
A Djz4780_dram.h18 #define DDRC_CTRL 0x8 macro

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