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Searched refs:DDRC_DBG0 (Results 1 – 3 of 3) sorted by relevance

/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c114 { DDRC_DBG0(0), 0x00000016 },
A Dlpddr4_timing.c79 { DDRC_DBG0(0), 0x00000016 },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h479 #define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300) macro

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