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Searched refs:DDRC_DBGCMD (Results 1 – 3 of 3) sorted by relevance

/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c116 { DDRC_DBGCMD(0), 0x00000000 },
A Dlpddr4_timing.c81 { DDRC_DBGCMD(0), 0x00000000 },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h482 #define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c) macro

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