Searched refs:DDRC_DFIMISC (Results 1 – 6 of 6) sorted by relevance
| /u-boot/drivers/ddr/imx/imx8m/ |
| A D | ddr_init.c | 158 clrsetbits_le32(DDRC_DFIMISC(0), (0x1f << 8), target_freq << 8); in ddr_init()
160 clrbits_le32(DDRC_DFIMISC(0), 0x1); in ddr_init()
197 setbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); in ddr_init()
214 clrbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); in ddr_init()
219 setbits_le32(DDRC_DFIMISC(0), 0x1); in ddr_init()
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| /u-boot/board/beacon/imx8mm/ |
| A D | lpddr4_timing.c | 49 { DDRC_DFIMISC(0), 0x00000011 },
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| /u-boot/board/freescale/imx8mm_evk/ |
| A D | lpddr4_timing.c | 49 { DDRC_DFIMISC(0), 0x00000011 },
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| /u-boot/board/freescale/imx8mq_evk/ |
| A D | lpddr4_timing_b0.c | 54 { DDRC_DFIMISC(0), 0x00000011 },
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| A D | lpddr4_timing.c | 52 { DDRC_DFIMISC(0), 0x00000011 },
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| /u-boot/arch/arm/include/asm/arch-imx8m/ |
| A D | ddr.h | 442 #define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) macro
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