Home
last modified time | relevance | path

Searched refs:DDRC_DFITMG2 (Results 1 – 5 of 5) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c41 { DDRC_DFITMG2(0), 0x0000170A },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c41 { DDRC_DFITMG2(0), 0x0000170A },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c55 { DDRC_DFITMG2(0), 0x0000170A },
A Dlpddr4_timing.c53 { DDRC_DFITMG2(0), 0x0000170A },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h443 #define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4) macro

Completed in 13 milliseconds