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Searched refs:DDRC_DFIUPD0 (Results 1 – 7 of 7) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c46 { DDRC_DFIUPD0(0), 0xE0400018 },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c46 { DDRC_DFIUPD0(0), 0xE0400018 },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c51 { DDRC_DFIUPD0(0), 0xE0400018 },
A Dlpddr4_timing.c49 { DDRC_DFIUPD0(0), 0xE0400018 },
/u-boot/board/toradex/colibri_imx7/
A Dimximage.cfg53 /* DDRC_DFIUPD0 */
/u-boot/board/novtech/meerkat96/
A Dimximage.cfg84 DATA 4 0x307A01A0 0x80400003 // DDRC_DFIUPD0
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h439 #define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0) macro

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