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Searched refs:DDRC_DRAMTMG0 (Results 1 – 7 of 7) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c24 { DDRC_DRAMTMG0(0), 0x1A201B22 },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c24 { DDRC_DRAMTMG0(0), 0x1A201B22 },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c33 { DDRC_DRAMTMG0(0), 0x1A201B22 },
A Dlpddr4_timing.c31 { DDRC_DRAMTMG0(0), 0x1A201B22 },
/u-boot/board/toradex/colibri_imx7/
A Dimximage.cfg75 /* DDRC_DRAMTMG0 */
/u-boot/board/novtech/meerkat96/
A Dimximage.cfg74 DATA 4 0x307A0100 0x090B1109 // DDRC_DRAMTMG0
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h413 #define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100) macro

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