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Searched refs:DDRC_DRAMTMG4 (Results 1 – 7 of 7) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c27 { DDRC_DRAMTMG4(0), 0x0F04080F },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c27 { DDRC_DRAMTMG4(0), 0x0F04080F },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c36 { DDRC_DRAMTMG4(0), 0x0F04080F },
A Dlpddr4_timing.c34 { DDRC_DRAMTMG4(0), 0x0F04080F },
/u-boot/board/toradex/colibri_imx7/
A Dimximage.cfg83 /* DDRC_DRAMTMG4 */
/u-boot/board/novtech/meerkat96/
A Dimximage.cfg78 DATA 4 0x307A0110 0x04020205 // DDRC_DRAMTMG4
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h417 #define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110) macro

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