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Searched refs:DDRC_DRAMTMG5 (Results 1 – 7 of 7) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c28 { DDRC_DRAMTMG5(0), 0x02040C0C },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c28 { DDRC_DRAMTMG5(0), 0x02040C0C },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c37 { DDRC_DRAMTMG5(0), 0x02040C0C },
A Dlpddr4_timing.c35 { DDRC_DRAMTMG5(0), 0x02040C0C },
/u-boot/board/toradex/colibri_imx7/
A Dimximage.cfg85 /* DDRC_DRAMTMG5 */
/u-boot/board/novtech/meerkat96/
A Dimximage.cfg79 DATA 4 0x307A0114 0x03030202 // DDRC_DRAMTMG5
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h418 #define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114) macro

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