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Searched refs:DDRC_FREQ1_DRAMTMG2 (Results 1 – 5 of 5) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c81 { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c81 { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c89 { DDRC_FREQ1_DRAMTMG2(0), 0x305080C },
A Dlpddr4_timing.c98 { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h545 #define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108) macro

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