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Searched refs:DDRC_FREQ1_INIT3 (Results 1 – 5 of 5) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c94 { DDRC_FREQ1_INIT3(0), 0x00840000 },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c94 { DDRC_FREQ1_INIT3(0), 0x00840000 },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c83 { DDRC_FREQ1_INIT3(0), 0x0140009 },
A Dlpddr4_timing.c111 { DDRC_FREQ1_INIT3(0), 0x00840000 },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h539 #define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc) macro

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