Home
last modified time | relevance | path

Searched refs:DDRC_FREQ1_RFSHCTL0 (Results 1 – 2 of 2) sorted by relevance

/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c81 { DDRC_FREQ1_RFSHCTL0(0), 0x0210000 },
131 { DDRC_FREQ1_RFSHCTL0(0), 0x00618040 },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h537 #define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050) macro

Completed in 8 milliseconds