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Searched refs:DDRC_IPS_BASE_ADDR (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h359 #define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00)
360 #define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04)
361 #define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08)
362 #define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10)
363 #define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14)
364 #define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18)
365 #define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c)
366 #define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20)
367 #define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24)
368 #define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28)
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A Dimx-regs.h62 #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) macro
/u-boot/arch/arm/mach-imx/mx7/
A Dpsci-mx7.c529 writel(0, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_enter_self_refresh()
530 while (readl(DDRC_IPS_BASE_ADDR + DDRC_PSTAT) & 0x10001) in imx_ddrc_enter_self_refresh()
533 writel(0x20, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_enter_self_refresh()
534 while ((readl(DDRC_IPS_BASE_ADDR + DDRC_STAT) & 0x23) != 0x23) in imx_ddrc_enter_self_refresh()
536 writel(readl(DDRC_IPS_BASE_ADDR + DDRC_PWRCTL) | 0x8, in imx_ddrc_enter_self_refresh()
537 DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_enter_self_refresh()
542 writel(0, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_exit_self_refresh()
543 while ((readl(DDRC_IPS_BASE_ADDR + DDRC_STAT) & 0x3) == 0x3) in imx_ddrc_exit_self_refresh()
545 writel(readl(DDRC_IPS_BASE_ADDR + DDRC_PWRCTL) | 0x1, in imx_ddrc_exit_self_refresh()
546 DDRC_IPS_BASE_ADDR + DDRC_PWRCTL); in imx_ddrc_exit_self_refresh()
A Dddr.c33 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR; in mx7_dram_cfg()
139 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR; in imx_ddr_size()
/u-boot/arch/arm/include/asm/arch-mx7/
A Dmx7-ddr.h119 #define DDRC_MP_BASE_ADDR (DDRC_IPS_BASE_ADDR + 0x03fc)
A Dimx-regs.h148 #define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000) macro

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