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Searched refs:DDRC_MSTR2 (Results 1 – 6 of 6) sorted by relevance

/u-boot/drivers/ddr/imx/imx8m/
A Dddr_init.c151 target_freq = reg32_read(DDRC_MSTR2(0)) & 0x3; in ddr_init()
/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c122 { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c122 { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c20 { DDRC_MSTR2(0), 0x00000000 },
A Dlpddr4_timing.c18 { DDRC_MSTR2(0), 0x00000000 },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h368 #define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28) macro

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