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Searched refs:DDRC_PCTRL_0 (Results 1 – 5 of 5) sorted by relevance

/u-boot/drivers/ddr/imx/imx8m/
A Dddr_init.c35 reg32_write(DDRC_PCTRL_0(0), 0x0); in ddrc_inline_ecc_scrub()
61 reg32_write(DDRC_PCTRL_0(0), 0x1); in ddrc_inline_ecc_scrub()
72 reg32_write(DDRC_PCTRL_0(0), 0x0); in ddrc_inline_ecc_scrub_end()
84 reg32_write(DDRC_PCTRL_0(0), 0x1); in ddrc_inline_ecc_scrub_end()
240 reg32_write(DDRC_PCTRL_0(0), 0x00000001); in ddr_init()
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c122 { DDRC_PCTRL_0(0), 0x00000001 },
A Dlpddr4_timing.c87 { DDRC_PCTRL_0(0), 0x00000001 },
/u-boot/board/novtech/meerkat96/
A Dimximage.cfg67 DATA 4 0x307a0490 0x00000001 // DDRC_PCTRL_0
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h517 #define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490) macro

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