Home
last modified time | relevance | path

Searched refs:DDRC_PERFHPR1 (Results 1 – 5 of 5) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c67 { DDRC_PERFHPR1(0), 0x04000030 },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c67 { DDRC_PERFHPR1(0), 0x04000030 },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c109 { DDRC_PERFHPR1(0), 0x5900575b },
A Dlpddr4_timing.c74 { DDRC_PERFHPR1(0), 0x5900575b },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h468 #define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c) macro

Completed in 12 milliseconds