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Searched refs:DDRC_SBRCTL (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/ddr/imx/imx8m/
A Dddr_init.c41 reg32_write(DDRC_SBRCTL(0), 0x00000014); in ddrc_inline_ecc_scrub()
45 reg32setbit(DDRC_SBRCTL(0), 0x0); in ddrc_inline_ecc_scrub()
55 clrbits_le32(DDRC_SBRCTL(0), 0x1); in ddrc_inline_ecc_scrub()
57 reg32_write(DDRC_SBRCTL(0), 0x100); in ddrc_inline_ecc_scrub()
59 reg32_write(DDRC_SBRCTL(0), 0x101); in ddrc_inline_ecc_scrub()
78 clrbits_le32(DDRC_SBRCTL(0), 0x1); in ddrc_inline_ecc_scrub_end()
80 reg32_write(DDRC_SBRCTL(0), 0x100); in ddrc_inline_ecc_scrub_end()
82 reg32_write(DDRC_SBRCTL(0), 0x101); in ddrc_inline_ecc_scrub_end()
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h527 #define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24) macro

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