Searched refs:DDRC_SCHED (Results 1 – 5 of 5) sorted by relevance

/u-boot/board/beacon/imx8mm/
A D	lpddr4_timing.c	65 { DDRC_SCHED(0), 0x29001701 },
/u-boot/board/freescale/imx8mm_evk/
A D	lpddr4_timing.c	65 { DDRC_SCHED(0), 0x29001701 },
/u-boot/board/freescale/imx8mq_evk/
A D	lpddr4_timing_b0.c	107 { DDRC_SCHED(0), 0x29511505 },
A D	lpddr4_timing.c	72 { DDRC_SCHED(0), 0x29511505 },
/u-boot/arch/arm/include/asm/arch-imx8m/
A D	ddr.h	466 #define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250) macro

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