Home
last modified time | relevance | path

Searched refs:DDRC_SWCTL (Results 1 – 4 of 4) sorted by relevance

/u-boot/drivers/ddr/imx/imx8m/
A Dddr_init.c31 reg32_write(DDRC_SWCTL(0), 0x00000000); in ddrc_inline_ecc_scrub()
63 reg32_write(DDRC_SWCTL(0), 0x00000001); in ddrc_inline_ecc_scrub()
70 reg32_write(DDRC_SWCTL(0), 0x00000000); in ddrc_inline_ecc_scrub_end()
86 reg32_write(DDRC_SWCTL(0), 0x00000001); in ddrc_inline_ecc_scrub_end()
155 reg32_write(DDRC_SWCTL(0), 0x00000000); in ddr_init()
163 reg32_write(DDRC_SWCTL(0), 0x00000001); in ddr_init()
191 reg32_write(DDRC_SWCTL(0), 0x00000000); in ddr_init()
200 reg32_write(DDRC_SWCTL(0), 0x00000001); in ddr_init()
211 reg32_write(DDRC_SWCTL(0), 0x00000000); in ddr_init()
225 reg32_write(DDRC_SWCTL(0), 0x00000001); in ddr_init()
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c117 { DDRC_SWCTL(0), 0x00000001 },
A Dlpddr4_timing.c82 { DDRC_SWCTL(0), 0x00000001 },
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h484 #define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320) macro

Completed in 10 milliseconds