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Searched refs:DDRC_ZQCTL0 (Results 1 – 7 of 7) sorted by relevance

/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c36 { DDRC_ZQCTL0(0), 0x03200018 },
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c36 { DDRC_ZQCTL0(0), 0x03200018 },
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c45 { DDRC_ZQCTL0(0), 0x03200018 },
A Dlpddr4_timing.c43 { DDRC_ZQCTL0(0), 0x03200018 },
/u-boot/board/toradex/colibri_imx7/
A Dimximage.cfg89 /* DDRC_ZQCTL0 */
/u-boot/board/novtech/meerkat96/
A Dimximage.cfg81 DATA 4 0x307A0180 0x00800020 // DDRC_ZQCTL0
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h431 #define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180) macro

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